DPLL Clock Recovery

Normally, the receive and transmit clock signals provide timing information for the receive and transmit data signals. This is the default API behavior. When an application does not allow for separate clock signals, the adapter's digital phase locked loop (DPLL) can recover the clock. The DPLL uses a reference clock and transitions on the received data signal (RxD) to recover the clock signal.

The following flags specify the clock source as the DPLL recovered clock or the internal baud rate generator (BRG) with the data rate specified in the ClockSpeed field of the MGSL_PARAMS structure.

HDLC_FLAG_RXC_DPLL Receive clock comes from DPLL (recovered)
HDLC_FLAG_RXC_BRG Receive clock comes from internal BRG
HDLC_FLAG_TXC_DPLL Transmit clock comes from DPLL (recovered)
HDLC_FLAG_TXC_BRG Transmit clock comes from internal BRG

The DPLL is essentially a clock generator that synchronizes itself to transitions on RxD. When RxD does not have any transitions for a long period of time, the DPLL recovered clock loses synchronization. It is necessary to maintain frequent transitions on RxD. NRZI-space encoding is well suited to DPLL applications because a zero is represented by a transition, and HDLC 0-stuffing guarantees a 0 bit every 6 bits. NRZ encoding can be used if the data contains sufficient transitions. Biphase encodings guarantee transitions every bit cell regardless of the data content and are the best choice for clock recovery

For most DPLL applications, HDLC_FLAG_RXC_DPLL and HDLC_FLAG_TXC_BRG are set and ClockSpeed is set to the expected data rate. This allows the receive clock to be recovered from the receive data signal. The transmit clock is taken directly from the BRG at the data rate specified in ClockSpeed. Operating the transmit clock independent of the recovered receive clock prevents propagation of clock jitter from the recovered signal to the transmit clock.

The reference clock for the DPLL is generated at ClockSpeed times the DPLL divisor. The DPLL divisor is specified with the following flags:

HDLC_FLAG_DPLL_DIV8 DPLL reference clock is 8 x ClockSpeed
HDLC_FLAG_DPLL_DIV16 DPLL reference clock is 16 x ClockSpeed
HDLC_FLAG_DPLL_DIV32 DPLL reference clock is 32 x ClockSpeed

Some adapters may not support all divisor options. Refer to the Adapter Features section for the divisors supported by a particular adapter.

Both the base data rate and DPLL reference clock are generated from the adapter oscillator frequency. Refer to the Adapter Features section for the oscillator frequency for each adapter type. The clocks are generated by dividing the oscillator frequency by a divisor which allows only specific data rates to be generated exactly. The relation for calculating the generated clock speed is:

DataRate = Oscillator Frequency/((16 bit integer time constant) + 1)

For a data rate to be created exactly, the data rate must be an even divisor of the oscillator frequency. DPLL applications require that both the base data rate and the DPLL reference clock (base rate times the DPLL divisor) be even divisors of the oscillator frequency.

Commonly used data rates that meet this requirement are 9600, 19200, 38400, 57600, and 115200 bits per second. A DPLL application that requires a data rate than cannot be exactly generated may still work if the difference between the exact rate and the actual rate is small enough and if a sufficient number of transitions on RxD are maintained.

DPLL and Biphase Encoding
When using biphase encoding, the DPLL stops providing clocks if two consecutive bit cells do not have transitions (code violations). The SyncLink PCI and SyncLink ISA adapters require 3 receive clocks following the last bit of a closing flag to properly identify the end of frame. Applications that do not provide an idle pattern between frames will prevent the DPLL from providing the required 3 clocks. This results in the received frame not being reported to the application until the DPLL regains synchronization.

Applications that require DPLL clock recovery with biphase encoding but cannot provide an idle pattern between frames should set both HDLC_FLAG_RXC_DPLL and HDLC_FLAG_RXC_BRG in the Flags member of the MGSL_PARAMS structure. This enables an option that detects a loss of DPLL synchronization, and temporarily switches the receive clock source to the BRG for 3 clock cycles before returning it to the DPLL. This provides the required 3 receive clocks following a closing flag to immediately recognize and report the received frame.

This option should not be used for any encoding other than biphase or when an idle pattern is provided between frames to maintain DPLL synchronization.

Previous Contents Next