HDLC Mode


HDLC (high level data link communication) is a serial protocol using data clocks operating at one clock cycle per bit (synchronous protocol). SDLC (synchronous data link communication) is a compatible subset of HDLC usually associated with IBM's legacy SNA networking. Details of HDLC are specified in the ISO 3309 standard.

Hardware peforms the following functions:

Framing
Boundaries of data (frames) are defined with special patterns called flags.

Transparency
Data patterns are differentiated from special patterns, such as flags, using a hardware function called zero bit stuffing and removal.

Error Checking
Data may be checked for errors with hardware generated CRC on transmit frames and hardware checked CRC on receive frames.

Sample HDLC data signal:

[... idle pattern ...][Flag][...Data...][CRC][Flag][... idle pattern...]

When not sending data, a hardware generated idle pattern is present on the data signal. This pattern is configurable and is usually all ones, or repeated flags. Hardware generates an opening flag before sending data. Hardware appends an optional CRC value and a closing flag to a frame of data. The application supplies only data, and the hardware generates flags and CRC. Only received data is returned to the application and the hardware removes flags and CRC.

In most applications, the leading bytes of data have special meaning. The first byte is usually the address field and the second byte is usually the control field. These fields are provided by the application to MgslTransmit. The API returns these fields to the application through MgslReceive. The use of these fields are application dependent. The API may be optionally configured to filter received frames based on a 8-bit address field.

A sequence of 7 or more contiguous ones is called an abort sequence. If an abort sequence is detected by the receiver after an opening flag but before a closing flag, the data is discarded and the receiver starts looking for the next opening flag. The hardware transparency function prevents sequences of 7 or more ones in the application data from being detected as an abort sequence.

Receiving Data

A disabled receiver ignores the receive data signal and never returns data to the application. When enabled. the receiver recognizes any non-flag pattern between two flags as a frame of data. If CRC is enabled, the hardware checks the CRC at the end of the data. Valid data is passed to the application as a single block (one frame) with CRC and flags removed.

The Data Carrier Detect (DCD) input signal may optionally be used as a hardware receiver enable. This is done by setting HDLC_FLAG_AUTO_DCD in the Flags field of the MGSL_PARAMS structure.

Sending Data

HDLC mode has three transmitter states: disabled, idle, active. When disabled, the transmit data signal is a constant mark. When idle (not sending data, but enabled), the transmitter sends a selectable idle pattern (usually ones or repeated flags). When active, the transmitter sends data provided by the application.

Each call to MgslTransmit sends one frame of data. The application provides only the data, and the hardware adds the flags, bit stuffing, and CRC.

The Clear to Send (CTS) input signal may optionally be used as a hardware transmit enable. This is done by setting HDLC_FLAG_AUTO_CTS in the Flags field of the MGSL_PARAMS structure.


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